![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)
Wake up :-)
by maresv on Sep 17, 2011 |
maresv
Posts: 22 Joined: Oct 28, 2008 Last seen: Jul 8, 2014 |
||
So what's the news folks?
|
RE: Wake up :-)
by marcus.erlandsson on Sep 17, 2011 |
marcus.erlandsson
Posts: 38 Joined: Nov 22, 2007 Last seen: Mar 7, 2013 |
||
We are debugging and verifying a new development board that are perfect to use as a demonstration board for the "OpenRISC ASIC"-FPGA design. It's a very small board with an Altera Cyclone IV FPGA and it has the following functions/interfaces:
- DDR2 - Ethernet - USB - SDHC - SPI Flash - FTDI USB (4 channels) - Two connectors (ex. PCI, LPC, AC97, GPIO) That's our status update, what's your? |
![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)